Fabrication

D. T. Yohannes et al., “Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics,” IEEE Transactions on Applied Superconductivity, vol. 25, no. 3, pp. 1–5, Jun. 2015, doi: 10.1109/TASC.2014.2365562.

Sergey K Tolpygo and Denis Amparo, “Fabrication-process-induced variations of Nb/Al/AlOx/Nb Josephson junctions in superconductor integrated circuits,” Supercond. Sci. Technol., 23, 2010, 034024
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D. Yohannes, A. Inamdar, and S. K. Tolpygo, “Multi-Jc (Josephson Critical Current Density) Process for Superconductor Integrated Circuits,” IEEE Trans. on Applied Superconductivity, vol. 19, no. 3, pp. 149-153, June 2009.

Sergey K. Tolpygo, Denis Amparo, Daniel T. Yohannes, Max Meckbach, and Alex F. Kirichenko, “Process-Induced Variability of Nb/Al/AlOx/Nb Junctions in Superconductor Integrated Circuits and Protection against It,” IEEE Trans. on Applied Superconductivity, vol. 19, no. 3, pp. 135-139, June 2009

Sergey K. Tolpygo, Diana Tolpygo, Richard T. Hunt, Supradeep Narayana, Yuri A. Polyakov, and Vasili K. Semenov, “Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits,” IEEE Trans. on Applied Superconductivity, vol. 19, no. 3, pp. 598-602, June 2009

Sergey K Tolpygo and Denis Amparo, “Electrical Stress Effect on Josephson Tunneling through Ultrathin AlOx barrier in Nb/Al/ALOx/Nb junctions, ” J. of Appl. Phys., 104, 063904, 2008
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Sergey K. Tolpygo, D. Yohannes, R. T. Hunt, J. A. Vivalda, D. Donnelly, D. Amparo, and A. F. Kirichenko, “20kA/cm^2 Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency,” IEEE Trans. on Applied Superconductivity, vol. 17, no. 2, pp. 946-951, June 2007.

Sergey K Tolpygo, Denis Amparo, Alex Kirichenko and Daniel Yohannes, “Plasma process-induced damage to Josephson tunnel junctions in superconducting integrated circuits,” Supercond. Sci. Technol., 20  S341-S349, (2007).
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Daniel Yohannes, Alex Kirichenko, Saad Sarwana, and Sergey K. Tolpygo, “Parametric Testing of HYPRES Superconducting Integrated Circuit Fabrication Processes,” IEEE Trans. on Applied Superconductivity, vol. 17, no. 2, pp. 181-186, June 2007

Daniel Yohannes, Saad Sarwana, Sergey K. Tolpygo, Anubhav Sahu, Yuri A. Polyakov, and Vasili K. Semenov, “Characterization of HYPRES’ 4.5 kA/cm^2 & 8 kA/cm^2 Nb/AlOx/Nb Fabrication Processes,” IEEE Trans. on Applied Superconductivity, vol. 15, no. 2, pp. 90-93, June 2005.

D. K. Brock, A. M. Kadin, A. F. Kirichenko, O. A. Mukhanov, S. Sarwana, J. A. Vivalda, W. Chen, and J. E. Lukens, “Retargeting RSFQ cells to a submicron fabrication process,” IEEE Trans. Appl. Supercond., vol. 11, no. 1, pp. 369-372, Mar. 2001

A.M. Kadin, C.A. Mancini, M.J. Feldman, and D.K. Brock, “Can RSFQ Logic Circuits be Scaled to Deep Submicron Junctions?,” IEEE Trans. Appl. Supercond., vol. 11, pp. 369-372, March 2001

A.M. Kadin, “A Phenomenological Model for High-Frequency Dynamics of Double-Barrier (SINIS) Josephson Junctions,” Supercond. Science & Technology, vol. 14, pp. 276-284 (May 2001)